CHAMP-FX3 (VPX6-472) 6U OpenVPX Virtex-6

CHAMP-FX3 (VPX6-472) 6U OpenVPX Virtex-6

The CHAMP-FX3 (VPX6-472) 6U OpenVPX FPGA processor card is the 3rd generation of user-programmable FPGA computing products from Curtiss-Wright Defense Solutions featuring the Xilinx Virtex-6 FPGA. It is designed to meet the needs of challenging embedded high-performance digital signal and image processing applications including Digital Beam Forming (DBF) and Synthetic Aperture Radar (SAR). The CHAMP-FX3 6U VPX FPGA processor board combines the dense processing resources of two large Xilinx V6 FPGAs with a powerful AltiVec-enabled dual-core Freescale Power Architecture MPC8640D processor on a rugged 6U OpenVPX-compatible (VITA 65) form factor module.

The rugged CHAMP-FX3 VPX processor balances the front-end processing capability with a collection of multi-gigabit rear-panel I/O and memories, including a Serial RapidIO® (sRIO)-based switching fabric, multiple, general-purpose high-speed serial links, and 20 pairs of LVDS links, per V6 FPGA to the backplane that can be used to support Camera Link or other high-speed parallel interfaces. The two FMC (FPGA Mezzanine Card) sites support the latest generation of FMC cards, such as the FMC-516 ADC FMC module, with 80 pairs of differential LVDS signals and connect directly to the onboard FPGAs for high bandwidth and low latency I/O. Each Virtex-6 FPGA processor supports both QDRII+ SRAMs and DDR3 SDRAMs. With four banks of 400 MHz QDR II+ memories for each SX475T FPGA, there is 25.6 GB/s of low latency memory bandwidth available on the CHAMP-FX3 6U VPX processor board. For larger data capture or transmission, there is 4 GB of 400 MHz DDR3 SDRAM available across 2 x32 banks per FPGA, providing 12.8 GB/s of memory bandwidth.

In addition to the hardware, Curtiss-Wright provides a full Software and FPGA Toolkit which includes either VxWorks 6.5/6.7 or WindRiver Linux APIs for all functions on the CHAMP-FX3 DSP FPGA platform. In addition FPGA IP cores, simulation models, testbench, test cases and documentation are provided to assist customers in integrating their DSP applications with the data processing cores on the CHAMP-FX3.

Curtiss-Wright recommends the CHAMP-FX4 for any new project designs.

  • 6U OpenVPX (VITA 65)
  • Dual user-programmable Xilinx Virtex-6 FPGAs (SX475T or LX550T), each with:
    • 2 GB DDR3 SDRAM in two banks
      • Supports migration to 4 GB per FPGA
    • 72 MB QDRII+ SRAM in four banks
  • Freescale Power Architecture MPC8640D processor
    • Running at 1 GHz
    • 1 GB SDRAM in two banks
  • Two Mezzanine sites with support for FMC (VITA 57)
  • On-board SRIO 1.3 switch
    • Four 4-lane fabric ports to the backplane
    • 4-lane ports to both user FPGAs and the MPC8640D processor
  • Thermal sensors for monitoring board temperatures
  • Sensors for monitoring board power consumption
  • Support for ChipScope™ Pro and JTAG processor debug interfaces
  • Multi-board synchronous clock
  • FusionXF BSP and FPGA design kit with highly-optimized IP Blocks, development environment, reference designs, scriptable simulation test benches and software libraries
    • VxWorks® and Linux® variants available
  • Continuum IPC - inter-processor communications middleware available
  • Continuum Vector subroutine library available
  • VITA 48 1” pitch format
    • Ruggedization levels
      • Level 0 (Commercial)
      • Air-cooled level 100
      • Conduction-cooled level 200
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